Circuit and method of a reference clock interface

ABSTRACT

The inventive circuit and corresponding method are used to form a universal referenece cycle interface for any synchronous source, whereby compensation processes and level compensations adaptively occur at decision thresholds.

CLAIM FOR PRIORITY

This application claims priority to PCT/DE00/03839, published in theGerman language on Jul. 12, 2001, which claims the benefit of priorityto German Application No. 199 63 804.7, filed in the German language onDec. 30, 1999.

TECHNICAL FIELD OF THE INVENTION

The invention relates to a circuit for generating at least one referenceclock.

BACKGROUND OF THE INVENTION

Clock generators, in particular for switching systems, have been builtusing submodules. In this case, the submodules are each designed forspecific reference clock types. With this design, each submodule hadonly one reference clock interface. Adaptation to a transmissionfrequency or a cable variant was otherwise achieved by manual setting; aspecification of alarm thresholds for level monitoring was achieved by aone-off setting, preferably during production of the submodules.

SUMMARY OF THE INVENTION

The invention discloses a circuit and a corresponding method to form areference clock interface.

The invention is advantageous since automatic adaptation to therespective reference clock type is performed and since settings for thecable variant are not required.

The invention is also advantageous since different input signals arerecognized, and for each input signal an adaptive threshold compensationfor sampling the input signal is formed.

A multiplicity of input signals can be used as an input signal, such asan atomic frequency, a PCM24 recovered signal, a PCM30 recovered signalor DS1 in BITS applications, without any further outlay for circuitryand without special settings during production. In one embodiment, it ispossible to derive from the input signal at least one first signal forderiving level information and threshold setting for a second signal,which serves at the same time as a trigger signal for the clockgenerator.

In one aspect, a continuous frequency and continuity monitoring can beperformed for both binary and ternary input signal types.

In another aspect, the frequency of the input signal is determinedautonomously and parasitic interference effects such as glitches anddropouts are selected.

The invention is also advantageous since with the quantization it issimultaneously possible to determine the jitter tolerance at which theselection of the parasitic interference effects is still ensured.

BRIEF DESCRIPTION OF DRAWINGS

Further features of the invention emerge from the detailed descriptionof the exemplary embodiments below with reference to drawings, in which:

FIG. 1 shows a structure of a reference clock interface.

FIG. 2 shows a mask.

FIG. 3 shows a mask.

FIG. 4 shows the incorporation of a reference clock interface in a clockgeneration unit.

FIG. 5 shows a block diagram.

FIG. 6 shows a circuit diagram.

DETAILED DESCRIPTION OF THE INVENTION

According to one embodiment of the invention, there is a universal,compensation-free reference clock interface, in particular for a clockgenerator in switching systems, which is described below along with acorresponding method.

FIG. 1 shows a structure of a universal reference clock interface havingan input IN+/IN−. The block diagram is divided into a first module B1and a second module B2.

Arranged in the first module B1, a “physical interface”, is atransformer U at which the input signal present on the primary side ofthe transformer U is divided on the secondary side into a first signalS1 and a second signal S2. The signal ES present on the input side ofthe transformer U may be a reference clock signal for example. A firstchannel K1, a so-called “level” channel, is fed the first signal S1, anda second channel K2, a so-called “trigger” channel, is fed the secondsignal S2. The level information (alarm criterion) is captured with thefirst signal S1; a triggering or sampling of the second signal S2 isperformed with the second signal S2 depending on the level informationobtained from the first signal S1. On the secondary side of thetransformer U is an overvoltage protector EMV and an impedance matchingelement (Za) in every channel, which together form a terminatingimpedance for the line connected to the input IN of the circuit.

Provided in the second module B2 are units for determining the requiredinformation with respect to the reference clock signal to be sampled andindividually provided. The second module B2 can also be designated anadaptive digital system. The analog signals supplied by the first moduleB1 on the first and second channel K1, K2 are digitized separately ineach case in the modules D1 and D2 in the second block B2. Arranged inthe modules D1 and D2 is a type of 1-bit analog/digital converter withan adaptively controlled decision threshold. The decision threshold issupplied with control signals, incl. clock signal, from a programmablelogic unit L, e.g. a programmable gate array. The programmable logicunit L enables the reference clock signal ES present at the input of thecircuit S to be acquired optimally with respect to sampling andmonitoring. The criteria obtained from the level information aredetermined with the aid of a processor subassembly arranged in thesecond module B2. The processor subassembly is formed by amicroprocessor μP and a module FW. A local clock generator SYS CLK makesclock and timing signals available for the reference clock interface.The second module B2 has a logic module L in which are integrated afirst processing unit V1 for adaptive level monitoring, a secondprocessing unit V2 for adaptive threshold setting for the first andsecond signal, and a third processing unit V3 for clock signaladaptation of the input signal ES. A clock signal conditioningcorresponding to the type of input signal is performed in the thirdprocessing unit V3.

In order to operate the reference clock interface with the differentstandardized cable variants, an optimized input impedance (cableconnection) is determined. When determining the input impedance, it isensured in accordance with international norm ITU-T G.703 that a returnloss of greater than 15 dB is maintained for both existing impedancetypes 75 and 120 ohm. From that an optimal input resistance ofapproximately 96 ohm for both impedance types can be derived, thus thereturn loss for both impedance types is approximately 18 dB. The inputresistance of 96 ohm also correlates with the terminating test impedancedefined in the American norm (Bellcore GR-499-CORE) of 100 ohm±5% for aDS1 pulse mask in the BITS applications.

It is particularly advantageous to use a broadband transformer U here.When a broadband transformer U is used, the input resistance can bemaintained in a wide frequency range, e.g. of 1.5 (10) MHz. It ispossible to connect to said circuit application all, for example, inputsignals of 1 MHz (atomic freq.), 1544 kHz (PCM24 recovered), 2048 kHz(PCM30 recovered), 5/10 MHz (atomic freq.) up to the 1.5 MB/s datasignals (DS1 with BITS applications) without any additionalconfiguration outlay.

The cable variants are defined in the cable connector by appropriatewiring of the inputs. Given a symmetrical 120 ohm cable, the two wiresare connected to the inputs IN+ and IN−. The cable shielding iscontacted to the GND terminal. Given coax cable applications, the signalwire of the coaxial cable is connected to IN+ and the cable shield ofthe coaxial cable is connected to GND. The inputs IN− and GND areshort-circuited in the cable connector.

By virtue of the compatibility achieved, both cable variants can beconnected to any reference clock inputs. As a result of a fixedrealization of the input resistance, when monitoring the level it isensured that, owing to the input impedance Rin=95 . . . 96 ohm, thelevel measured is increased by approximately 11% for 75 ohm applications(with coax cable) and reduced for 120 ohm applications (with symm.cable).

The requirements for digitization and the control thereof will beexplained with reference to the signal mask shown in FIG. 2 inaccordance with ITU-T G.703 for 2048 kHz, and the Bellcore GR-499-COREsignal mask for 1.5 MB/s synchronization signals shown in FIG. 3. Toenable comparison of the two masks shown in FIGS. 2 and 3 with oneanother, only the upper halves of the pulse are represented in eachcase.

The two systems according to ITU-TG.703 and Bellcore GR-499-Core exhibitfundamental differences. A mask (T3 mask) as shown in FIG. 2 areobserved directly at the output of a synchronization source. The maskwas designed for a sinusoidal signal or a digital clock signal(two-value signal). A first decision threshold P and a second decisionthreshold Q for a hysteresis are defined for the level monitoring (alarmdetection). The second decision threshold represents an alarm switch-onthreshold for a level failure. If the level at the reference clock inputfalls below the second decision threshold, a loss of signal alarm istriggered and at the same time the second decision threshold isincreased to the potential of the first decision threshold P. When thereference clock signal returns, the level alarm is then withdrawn here,and the decision threshold is again lowered to the Q level. There is asufficient gap (hysteresis) between the levels P and Q in order toensure the unambiguity of the alarm triggering at all times even in thecase where the level is fluctuating and subject to interference. Toogreat a hysteresis sets the Q level very low. As a result, referenceclock signals having too low a level are still accepted, which isdisadvantageous since too low a level is prone to interference and inaddition causes increased jitter during digitization.

In a building integrated time source BITS system, in contrast to the T3mask, the pulse mask is controlled at the system input DDF (digitaldistribution frame), which means that the connection cable is includedin the check. Existing systems are designed for cable attenuation up to6 dB. The criterion for a level failure is defined on the digital sideby the evaluation of the spectral density following sampling. Thismethod requires an adaptive comparator compensation (approx. 50% of thepresent amplitude). As shown in FIG. 3, the mask was designed for a B8ZScoded data signal (ternary signal).

Table 1 shows a summary of the alarm criteria in comparison between thetwo abovementioned signal types (system). Supplementary thereto, Table 2shows the norm requirements according to ITU-T G.775 and an actualrealization approach with discrete thresholds for both signal types.

TABLE 1 Alarm criteria Level of System Alarm on Alarm off evaluation T3Q level not P level Analog 2048 kHz reached exceeded For 5 . . . 124 μsFor 5 . . . 124 μs BITS Signal density < Signal density = Digital 1544kB/s 12.5% 12.5% for 65 . . . 162 μs for 65 . . . 162 μs

TABLE 2 Alarm thresholds Norm System requirement Realization approach T3P: = −9 dB¹ 0.47 V −12.6 dB/Zo = 75Ω −14.8 dB/Zo = 120Ω Zo = 75/120Ω Q:= −35 dB¹ 0.23 V −20.8 dB/Zo = 75Ω −23.0 dB/Zo = 120Ω BITS Adaptive: 50%0 dB threshold: 1.70 V (4.4 V³) Zo = 100Ω of amplitude −3 dB threshold:1.15 V (3.4 V³) value² −6 dB threshold: 0.85 V ¹Relative to nominallevel ²The norm does not require any analog-side monitoring ³Transitionto next lower level

With 75 Ω and 120 Ω cable, the limit values P and Q for T3 producedifferent thresholds because a uniform signal power is assumed for thedefinition. For this reason the relative norm specifications are given.The fixed thresholds (the same for both impedances) used in therealization approach are well within the permitted limits (seecomparison in dB). The mismatch was already taken into account in theconversion with ±1 dB. The hysteresis is approx. 240 mV.

In order to achieve sufficient safety clearance to the interferencelevel, the reference signal is transformed up by 1:2 on the “level”channel. Since the norm specifies the amplitude in Vos, the alarmthreshold in V can be simply compared with the associated level in Vss1:1. The reference signal is transmitted 1:1 and forwarded to thedigitization stage on the “trigger” channel. For T3 reference signalsthe threshold is 0 V (signal center).

In conjunction with a downstream pulse width control, according to theinvention the discrete BITS limit values, in this case: 0 dB, −3 dB and−6 dB (relative to the nominal level), satisfy the prerequisites for anoptimal bit error-free sampling of the 1.5 MB/s synchronization signals.

The control for the threshold definition for BITS applications isperformed in an adaptive manner, such that the amplitude is comparedwith the threshold 4.4 V on the “level” channel. This measured valuecorresponds to a level 2.7 dB below the nominal value of 3.0 Vosaccording to ITU-T G.703. The associated 0 dB trigger threshold is at1.70 V (approximately 50% of the maximum amplitude of 3.6 Vos. If thelevel is insufficient, a switch is made to the next lower level value of3.4 V (corresponds to −5 dB). This includes the −3 dB trigger thresholdwith 1.15 V (corresponds to approx. 50% of the 0 dB limit with 4.4 V).If the level is still not sufficient, the trigger threshold is loweredto the −6 dB limit with 0.85 V (corresponds to exactly 50% of the −3 dBlimit with 3.4 V). The lowest trigger threshold corresponds to an analogside input sensitivity of −11 dB (−9 dB) relative to the nominal level(minimum permitted level). In particular the negative overshoot of thereference signal was taken into account when optimizing the discretethresholds, so that no sampling of this signal segment can occur at anylevel value.

A downstream pulse width check is intended to detect and filter outconfigured signal segments (pre-equalization) and increased cablereflections.

With this method, for example in the case of a ternary BITS signal, thepositive pulse halves are detected and the synchronization offered.

FIG. 4 shows an incorporation of a reference clock module ER in acentral clock generator CCGES. This representation shows the modulesconnected to a processor P of the clock generator. In this case, theprocessor is connected for example via a bus connection to the logicmodule L and to a storage module SM. A time base unit ZB supplies boththe clock pulse for the processor P, the logic module L and thereference clock module ER. The logic module L is connected to amultiplicity of interface units 2 to n. The first interface unit 1 willbe explained in greater detail with reference to the figures and theassociated descriptions described. With this circuit, the functionalityof the circuit of the logic module L, a programmable module, e.g. afield programmable gate array (FPGA), is provided in connection with theprocessor P.

An interaction of a first or second unit D1, D2 with a programmablelogic unit downstream thereof is explained in FIG. 5. The interfacebetween the analog and digital part of the circuit is formed in eachcase by a comparator K which can be integrated for example in a modulewith the designation MAX916. In a refinement of the invention, thecomparator K, a dual 1-bit analog/digital converter, has a high inputsensitivity (approx. 2 mV) as well as a high processing speed of up to50 MS/s for better processing of the analog signals applied. An extendedinput voltage range of ±5 V permits use for standardized reference clocksignals. A 40 MHz quantization clock already ensures a reliable samplingof reference frequencies between 1 and 10 MHz.

The reference voltages Uref,_(1,2) for the first and second signal S1,S2 are supplied by the programmable logic unit L via a low-pass filterLF. The low-pass filter smooths here the voltage jumps coming from thedigital/analog converter (threshold switchover) and also the suppressionof a.c. voltage components such as noise levels, ripple, etc. Thedynamic properties of the low-pass filter LF are determined by the timeparameters of the alarm criteria. The time parameters for, for example,a level alarm were set uniformly for both systems (T3 and BITS) to 100μs. To reach the steady-state condition quickly and at the same timeobtain the greatest possible low-pass effect, a short low-pass timeconstant of approximately 5 μs is selected.

The digital/analog converters DAC are part of the programmable logicunit L. Two methods for analog voltage generation for continuous valuecontrol by means of the DC content implemented in the pulse width can beconsidered here by way of example. With a first method, the valuescaling is determined by the height of the quantization frequency. Theadvantages of this method lie in the increased flexibility of theadaptive threshold control and in the fact that the low-pass filter iscontrolled via one line. This saves on external components, pins andspace.

The second method realized in the exemplary embodiment permits adiscrete value control limited to a few values by means of a pluralityof static control symbols from the programmable logic unit. According toTable 2, three discrete voltage values per channel (level and trigger)are preferably used to ensure the level detection function for referenceclock signals. Two control signals with three possible logic states (L,H and high Z) are required for this. The advantage of this method isthat no great demands are placed on the programmable logic unit withrespect to the dynamic, and no residual ripple overlays the referencevoltage.

The first and second signals supplied by the comparator stage K aresubjected to a digital filtering dF to enable a correct evaluation ofthe digitized analog signals. The circuit according to the inventionautonomously determines the frequency of the connected reference clocksignals and selects parasitic interference effects such as glitches anddropouts for example. As a result of the quantization, the jittertolerance at which the selection of the parasitic interference effectsstill functions reliably is simultaneously determined.

The input frequency is checked and selected in accordance with Table 3on the basis of the number of 40 MHz quantization clock periods perreference clock period.

TABLE 3 Reference freq. 10 MHz 5 MHz 2048 kHz 1544 kHz 1 MHz BITS Number3 7 18 24 38 48 min. Number 4 8 19.5 25.9 40 51.8/ nom. 77.7¹ Number 5 921 28 42 84 max. Frequency 8.00 . . . 4.444 . . . 1905 . . . 1429 . . .0.952 . . . 1429 . . . band 13.333 5.714 2222 1667 1.053 1667 kB/sJitter 25 ns 25 ns 37 ns 48 ns 50 ns 144 ns tolerance ¹Frame gap in 1.5MB/s “all ones” BITS signal

Another function of the digital filtering dF is the checking of thepulse width of the reference clock signals coming from the comparatorstage. A spike suppression is performed on the trigger channel and thecorrect phasing on upper pulse halves of the BITS signals wherereflections are present on the cable connection to the reference clockinterface.

The control logic SL of the logic module L performs the adaptivethreshold control of the comparator stage K via the μP interface bymaking control signals for generating the reference voltages availableto the comparator stage. Furthermore the quantization clock is offeredphase-adjusted by the clock block CLK taking account of the propagationdelay conditions of the I/O cells.

The forwarding of the digitally filtered reference clock signals(“trigger” channel) and the level measurement signals on the first“level” channel to the μP interface is likewise performed by means ofthe control logic SL.

The μP interface establishes the connection between the programmablelogic unit L and the processor subassembly μP and FW, as shown inFIG. 1. Non time-critical mathematical operations and time measurementsare performed by the μP itself. These include the determination of thealarm criteria as well as the coding for adaptive threshold control.

In this development, the universal reference clock interface includingfour identically structured channels in accordance with the circuitdiagram shown in FIG. 6. Shared for four channel's the programmable gatearray, e.g. FPGA:XC4044XLA which, apart from the interface functions,combines in itself all time-critical HW components of the central clockgenerator CCGES.

Connected to the control outputs L1,2 and T1,2 is a simple DAC(digital/analog converter) including low-pass filter (LF) comprised ofRC components. The low-pass effect at the outputs Uref1 and Uref2 isvariable due to the control with 3-value code. Matched to the normrequirements, the code-dependent time constants lie in the range of 0.5. . . 10 μs. The coding with the assignment to the various thresholds isshown in Table 4.

TABLE 4 Coding of the threshold control realized in FIG. 6 Levelcomparator Trigger comparator System Designation L1 L2 U_(ref1) T1 T2U_(ref2) T3 P L Z 0.47 V L L 0 V Q L L 0.23 V L L 0 V BITS  0 dB Z Z 4.4V  H H 1.70 V −3 dB H H 3.4 V  L H 1.15 V −6 dB — — — H Z 0.85 V

The comparator K is operated with 30 5 V supply voltage. The digitalinputs and outputs (CLK_(A,B) and Q_(A,B)) work with TTL level so that adirect connection to the first module in LV-CMOS with 3.3 V is possiblewithout level adaption. The connection lines are HF-matched serially bymeans of resistors, for example 33 ohm. The high-resistance analoginputs of the MAX916 (level and trigger) are protected againstovervoltage peaks by the resistors R4, R5 with 330 ohm resistance each,since the internal clamp diodes allow limited current peaks.

The two resistors R2, R3, for example 215 ohm, together with a resistorR1, for example 1 kohm, (directly at their input) realize the optimalimpedance matching (Za, FIG. 1) of the reference clock inputs for 95.96ohm. The two LCDA05 modules from the firm of Semtech ensure sufficientovervoltage protection (ESD, EFT) with the aid of integrated suppressordiodes (TVS array). Owing to the integration of serial Schottky diodesin this chip, a very low load capacitance is achieved, whichsignificantly improves the HF properties of the reference clockinterfaces.

The last module is the interface transformer T1068 from the firm ofPulse. This octal toroidal core transformer in SMD assembly technologyhas been specifically developed for the 1.5 MB/s and 2 MB/s data rate.It includes four transformers with ü=1:1 (CT) and four with ü=1:2 (CT).Owing to the excellent HF properties up to about 5 MHz, the fourup-transforming transformers are ideally suited for use in the referenceclock inputs. The function can be extended to 10 MHz, in which case aworsening of the input reflection by up to 6 dB is accepted.

1. A circuit for generating at least one reference clock, comprising: afirst module to form a physical interface, with at least one of a firstand second signal being formed from an input signal present at the inputof the first module; a second module to monitor the first signal and todetermine adaptation parameters for a sampling of the second signal,wherein the first module has a transformer by means of which the inputsignal present at its primary winding is divided on the secondary sideinto the first and second signal, and the second module has a firstprocessing unit for adaptive level monitoring, a second processing unitfor adaptive threshold setting for the first and second signal, and athird processing unit for clock signal adaptation of the input signal.2. The circuit as claimed in claim 1, wherein a corresponding clocksignal conditioning is performed by the third processing unit, dependingon the input signal.
 3. A method for generating at least one referenceclock, comprising: forming a physical interface in a first module, withat least one of a first and second signal being formed from an inputsignal present at the input of the first module; monitoring the firstsignal and determining the adaptation parameters for an optimal samplingof the second signal in a second module, wherein the first and secondsignals are formed from the input signal in the first module, such thatan adaptive level monitoring of the input signal is performed in thesecond module, an adaptive threshold setting for the first and secondsignal is performed, and a clock signal adaptation of the input signalis performed.
 4. The method as claimed in claim 3, wherein acorresponding clock signal conditioning is performed depending on theinput signal.